1. Field of the Invention
One embodiment of the present invention relates to a semiconductor device, a method for driving the semiconductor device, and the like.
The technical field of one embodiment of the invention disclosed in the specification, the drawings, and the claims (hereinafter referred to as “this specification and the like”) is not limited to the above-described technical field. One embodiment of the present invention relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. The technical field of one embodiment of the present invention, for example, includes devices such as a semiconductor device, a display device, a light-emitting device, a lighting device, a storage device, and a memory device; methods for driving the devices, and methods for manufacturing the devices.
2. Description of the Related Art
A problem of increase in static power consumption due to a leakage current arises with miniaturization of transistors in semiconductor devices. As a technique for reducing power consumption of semiconductor devices, a clock gating technique which stops input of a clock signal to a circuit that is not necessary for operation, and a power gating technique which blocks power supply are known. With the clock gating, dynamic power consumption can be reduced but static power consumption cannot be fully reduced.
A clock tree for supplying one clock signal to a plurality of circuits is used. For example, controlling the supply of power supply potentials to logic gate circuits included in a clock tree has been suggested for a reduction in a leakage current of the clock tree (see Patent Documents 1 to 3).
A variety of semiconductor devices that use a transistor including an oxide semiconductor in its semiconductor region (hereinafter referred to as “OS transistor”) have been suggested. For example, by using an OS transistor as a transistor that is turned off in a standby mode, standby power of a logic circuit can be reduced (see Patent Document 4).